1. Field of the Invention
The invention relates to a receiving apparatus for receiving a spread spectrum signal.
2. Related Background Art
In a spread spectrum communication, a clock signal synchronized with data which is transmitted to demodulate a signal and a code timing need to be extracted on the demodulation side.
For this purpose, a convolution integration of a reception signal and the same PN (pseudo noise) code as that of the reception signal which was generated on the demodulation side is executed by an analog convolution integrator such as convolver, matched filter, or the like of an SAW (surface acoustic wave) device, and a clock signal and a code timing is extracted from an output of the analog convolution integrator.
FIG. 18 shows a conventional sync circuit using a convolver. A high frequency unit 21 converts a reception signal to an intermediate frequency and outputs to a convolution integrator 11B. A sync clock is reproduced by using a PLL (phase locked loop) circuit which inputs a signal indicative of a peak value timing of a signal extracted from an output of the convolution integrator 11B through a timing extraction circuit 12B and which is constructed by a phase comparator 14X, a loop filter 14Y, a sample holder 14Z, a voltage controlled oscillator (VCO) 13B, and a code generator 16B. The PLL is locked with a peak value timing of an input and a clock synchronization and a code timing synchronization are established. To hold such a state, the sample holder 14Z is set to a holding mode, thereby holding an input voltage of the VCO. By holding an input voltage of the VCO, a synchronization with the data is held and a demodulation unit 23 reproduces data by using a sync clock.
In the conventional apparatus, however, since the VCO output becomes a clock for reproduction upon reproduction of the data, it is necessary to select an output whose phase noises (jitter) are enough small for a clock frequency. Since there is a trade-off relation between a gain (output frequency/input voltage) of the VCO 13B and the jitter, a level of the gain is limited. A pull-in speed of the PLL is restricted by the limitation of the gain, so that a data transmitting speed deteriorates.
Since the sample holder 14Z by the analog circuit is used to hold the VCO input voltage, error factors such as holding step, droop characteristics, and the like occur and it is difficult to hold accurate frequency and phase for a long time in a data interval. The maximum length, therefore, of the data is limited.